Altium

Design Rule Verification Report

Date: 28.06.2017
Time: 14:35:04
Elapsed Time: 00:00:02
Filename: C:\Users\akos\Documents\LoRa\pcb\LoRa+WUR Sensors Node V3.0\PCB.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=5mil) (InNet('NetJ4_1')),(All) 0
Clearance Constraint (Gap=12mil) (InPolygon),(All) 0
Clearance Constraint (Gap=6mil) (All),(All) 0
Clearance Constraint (Gap=5mil) (InNet('NetJ2_1')),(All) 0
Clearance Constraint (Gap=5mil) (InNet('NetJ1_1')),(All) 0
Clearance Constraint (Gap=11.811mil) (InNetClass('RF')),(InPolygon) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (InNet('D_GND')),(InNetClass('RF_GND')) 0
Short-Circuit Constraint (Allowed=Yes) (InNet('No Net')),(InNet('No Net')) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=5.905mil) (Max=98.425mil) (Preferred=10mil) (All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=31.496mil) (PreferredHoleWidth=11.811mil) (MinWidth=17.716mil) (MaxWidth=47.244mil) (PreferedWidth=23.622mil) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (IsVia) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=8mil) (Air Gap=8mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=5.905mil) (Disabled)(All) 0
Hole Size Constraint (Min=7.874mil) (Max=275.591mil) (All) 0
Minimum Solder Mask Sliver (Gap=3.898mil) (All),(All) 0
Silk To Solder Mask (Clearance=3.937mil) (IsPad),(All) 0
Silk to Silk (Clearance=3.937mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Length Constraint (Min=2994mil) (Max=3006mil) (InNetClass('Tektronic')) 0
Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (Disabled)(All),(All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (Disabled)(All) 0
Total 0